1. Field of the Invention
The present invention relates to a fabrication method of semiconductor integrated circuit device, and more particularly, to a fabrication method of a semiconductor integrated circuit device with a patterned field oxide formed on a semiconductor substrate by selective oxidation.
2. Description of the Prior Art
With semiconductor integrated circuit devices of this type, an isolation region is generally provided to isolate adjacent elements or components such as transistors from each other. As a technique to form the isolation region, a selective oxidation technique called "Local Oxidation of Silicon (LOCOS)", in which a semiconductor substrate is locally oxidized to form the patterned field oxide film, has been chiefly used in most of the semiconductor integrated circuit devices.
As an example of the conventional fabrication methods of the semiconductor devices of this type, a fabrication method of a NAND-type mask Read Only Memory (ROM) device using the LOCOS technique is described below. FIG. 1 is a plan view showing part of a memory cell array of the mask ROM device, and FIGS. 2A to 2J are cross-sections along the line II--II in FIG. 1 showing the fabrication process steps of the ROM device, respectively.
The memory cell array contains a plurality of Metal-Oxide-Semiconductor (MOS) transistors and a plurality of capacitors arranged in a matrix array on a p-type silicon substrate 101. On the substrate 101, there are a plurality of isolation lines 107 formed by a field oxide film patterned to linear shapes and a plurality of word lines 114. The field oxide film 107 is made of silicon dioxide (SiO.sub.2). The word lines 114 are made of stacked polysilicon and tungsten silicide (WSi.sub.2) films 112 and 113 patterned to linear shapes, respectively. The isolation lines 107 and the word lines 114 are perpendicular to each other.
The isolation lines 107 define active regions 106 in the surface area of the substrate 101. Each of the active regions 106 is between adjacent two of the isolation lines 107. The isolation lines 107 also define inactive regions 105 in the surface area of the substrate 101. Each of the inactive regions 105 is disposed under each of the isolation lines 107. The word lines 114 serve as gate electrodes of the MOS transistors in the corresponding active regions 106, respectively.
Each of the memory cells contains MOS transistor and a capacitor, both of which are provided in corresponding one of the active regions 106. The MOS transistor is composed of a pair of source/drain regions 115 formed in corresponding active region 106 and a gate electrodes 114 disposed on the substrate 101 through a gate oxide film 111. The pair of the source/drain regions 115 are here formed of N.sup.+ -type diffusion regions disposed at respective sides of a corresponding word line 114. A channel area is formed under the gate electrode 114 between the pair of the source/drain regions 115 in the active region 106.
Coded MOS transistors of the memory cells are of the enhancement (normally off) type, and uncoded MOS transistors are of the depletion (normally on) type. In the channel areas of the depletion-type MOS transistors, n-type diffusion regions 116 are provided to form channels therein by ion-implantation or the like, respectively.
The memory cell array of the mask ROM device described above is fabricated by the following process steps:
First, as a pad oxide film 102, a silicon dioxide (SiO.sub.2) film with a thickness of about 400 .ANG. is grown on the entire surface of the p-type silicon substrate 101. A silicon nitride (Si.sub.3 N.sub.4) film 103 with a thickness of about 1200 .ANG. is then formed on the pad oxide film 102 entirely, as shown in FIG. 2A. A photoresist film 104 is formed on the silicon nitride film 103 and the film 104 is patterned to have openings or windows 104a at positions corresponding to the respective inactive regions 105, as shown in FIG. 2A.
Next, using the patterned photoresist film 104 as a mask, the silicon nitride film 103 is selectively removed by etching to form openings or windows 103a, as shown in FIG. 2B. At this time, the surface area of the pad oxide film 102 is also partially etched at positions under the respective windows 103a. The patterned photoresist film 104 is then removed. Using the patterned silicon nitride film 103 as a mask, the surface area of the silicon substrate 101 is selectively, thermally oxidized to form a thick silicon dioxide (SiO.sub.2) film in the inactive regions 105 as the field oxide film 107, as shown in FIG. 2C. The pad oxide film 102 is incorporated into the field oxide film 107 during this process.
The patterned silicon nitride film 103 is then removed by etching using phosphoric acid or the like. At this time, as shown in FIG. 2D, the field oxide film 107 thus selectively formed has steps or protrusions 108 produced at both sides of the film 107 near the patterned silicon nitride film 103, which means that "the bird's head phenomenon" arises.
Subsequently, the pad oxide film 102 remaining in the active regions 106 is removed by etching using hydrofluoric acid so that the surfaces of the active regions 106 are exposed, as shown in FIG. 2E.
The substrate 101 is then subjected to heat-treatment under an oxygen atmosphere so that a silicon dioxide film 110 with a thickness of about 200 .ANG. is selectively formed on the active regions 106, as shown in FIG. 2F. During this process, the field oxide film 107 is also grown.
To adjust the threshold voltages of the n- and p-channel MOS transistors provided in the peripheral circuitry (not shown) of the ROM device, dopant ions are implanted into the substrate 101.
Then, the silicon dioxide film 110 formed in the active regions 106 is selectively removed by etching using hydrofluoric acid or the like so that the surfaces of the active regions 106 are exposed, as shown in FIG. 2G. During this process, the surface of the field oxide film 107 is also etched.
The substrate 101 is then subjected to heat-treatment under an oxygen atmosphere again so that a silicon dioxide film 111 with a thickness of about 200 .ANG. is selectively formed on the active regions 106 as the gate oxide film, as shown in FIG. 2H.
The polysilicon film 112 with a thickness of about 1000 to 2000 .ANG. and the tungsten silicide film 113 with a thickness of about 1000 to 2000 .ANG. are successively formed to cover the entirety of the substrate 101. Thus, the gate oxide film 111 formed on the active regions 106 and the field oxide film 107 formed on the inactive regions 105 are covered with the films 12 and 113, as shown in FIG. 2I.
The polysilicon film 112 and the tungsten silicide film 113 are patterned to form the gate electrodes 114 acting also as the word lines by dry etching. At this time, since the cross--section along the line II--II in FIG. 1 is parallel to the word lines 114, the films 112 and 113 do not appear in FIG. 2J.
Thereafter, using the patterned field oxide film 107 and the gate electrodes 114 as a mask, arsenic ions are selectively implanted into the respective active regions 106 to form the pairs of the n.sub.+ -type source/drain regions.
Finally, a photoresist film (not shown) is formed to cover the entirety of the memory cell array. The photoresist film is then patterned to have windows at positions corresponding to the channel areas of the MOS transistors to be coded. Phosphorus ions are selectively implanted into the channel areas to form the n-type coded diffusion regions 116 through the corresponding gate electrodes 114.
With the fabrication method of the mask ROM device described above, the steps or protrusion 118 are produced on the field oxide film 107 due to the "bird's head phenomenon". Therefore, during the process step of forming the gate electrodes and the word lines 114 by patterning the tungsten silicide film 113 and the polysilicon film 112, the polysilicon film 112 is difficult to be etched satisfactorily due to the steps 108.
As a result, there is a problem that leavings 112a of the polysilicon film 112 are easy to be generated along the steps 108, as shown in FIG. 2J, giving short-circuit between the gate electrodes and/or the word lines 114.
If the polysilicon film 112 is removed satisfactorily during the above etching process in order to solve this problem, there arises another problem that the surfaces of the active regions 106 are to be damaged because the thin gate oxide film 111 is easy to be etched during the etching process.